1. Technical Field
The present invention generally relates to a multiprocessor system bus protocol, and, in particular, a multiprocessor system bus protocol with group addresses, responses, and priorities. Still particularly, the present invention relates to a multiprocessor system bus protocol wherein snoop responses are grouped into different types of responses and managed and handled by the groups.
2. Description of the Related Art
A computer program executed by multiple processors typically needs to have the same copies of data in various cache memory devices. The performance of the computer program executed by multiple processors is directly related and dependent on the performance of sharing data by the system. Multiprocessor cache coherency must be maintained in order to reduce bus traffic. xe2x80x9cCache-coherency protocolsxe2x80x9d are protocols used to maintain coherency among multiple processors. One class of cache-coherency protocol that is used to maintain cache coherency is xe2x80x9csnoopingxe2x80x9d. xe2x80x9cSnoopingxe2x80x9d generally involves every cache that has a copy of data from a memory block (i.e. physical memory) also possessing a copy of information about that data. The caches are typically on a shared-memory bus. Each cache controller monitors or xe2x80x9csnoopsxe2x80x9d on the bus to determine whether or not they have a copy of the shared block. The coherency problem involves the processor exclusively accessing the write function of an object and making sure that it has the most recent copy when performing a read function of an object. All caches sharing the object to be written must be located by the snoop protocol. When a write-to-shared data operation occurs, the decision of whether to invalidate all other copies or to broadcast the write to all shared copies must be made. These above concepts are developed and disclosed in the text entitled Computer Architecture A Quantitative Approach, by David A. Patterson and John L. Hennessy, Morgan Kaufmann Publishers, San Mateo, Calif., Copyright 1990.
A request of data in a memory block(s) is made by the computer program. All caches respond to the request with a xe2x80x9csnoop responsexe2x80x9d in order to take appropriate action and/or execute the response to the request. Computer systems, of course, may have a number of cache memory devices. Managing these cache memory devices and their respective snoop responses may become quite a task, especially if a large number of cache devices exist and/or if the number of snoop responses is or is becoming voluminous.
For example, the memory device has to individually send each snoop response to a respective location, and the combined response logic system has to handle each and every snoop response. Various types of snoop responses exist and are well known in the art, and different types of snoop responses are handled in different ways. The manner in which a large number of snoop responses that are handled by a combined response logic system would result in at least two key problems. One problem is that the bus or wire from a memory device to the combined response logic system and the bus or wire from the combined response logic system to the memory device may have to be made larger in size (i.e. in bit size) to accommodate all of the various snoop responses. Another problem is that the combined response logic system may be slowed down and become very inefficient in having to receive and handle each snoop response for generating a combination response (especially if a large number of responses are provided by the memory devices) for the memory devices.
It would be advantageous and desirable to provide a system and method for better managing and handling snoop responses, particularly large number of snoop response, and respective combined responses in a multiprocessor system bus protocol or snoop protocol wherein the combined responses and snoop responses are generally between memory devices and a combined response logic system. It would also be advantageous and desirable to provide a system and method that minimizes and/or reduces the size of the bus or wire between each memory device and the combined response logic system wherein a snoop response is sent from each memory device to the combined response logic system. It would also be advantageous and desirable to provide a system and method that minimizes and/or reduces the size of the bus or wire between the combined response logic system and each memory device wherein a combined response is sent from the combined response logic system to each memory device. It would further be advantageous and desirable to provide a system and method that provides faster and more efficient handling of snoop responses by a bus master and the combined response logic system. Thus, it is advantageous and desirable to provide a multiprocessor system bus protocol wherein snoop responses are grouped into different types of responses and the groups are thereby managed and handled.
It is therefore one object of the present invention to provide a system and method for better managing and handling snoop responses and respective combined responses in a multiprocessor system bus protocol or snoop protocol wherein the combined responses and snoop responses are generally between memory devices and a combined response logic system.
It is yet another object of the present invention to provide a system and method that minimizes and/or reduces the size of the bus or wire between each memory device and the combined response logic system wherein a snoop response is sent from each memory device to the combined response logic system.
It is yet another object of the present invention to provide a system and method that minimizes and/or reduces the size of the bus or wire between the combined response logic system and each memory device wherein a combined response is sent from the combined response logic system to each memory device.
It is another object of the present invention to provide a system and method that provides faster and more efficient handling and managing of snoop responses by a bus master and the combined response logic system.
It is a further object of the present invention to provide a multiprocessor system bus protocol wherein snoop responses are grouped into different types of responses and the groups are thereby managed and handled.
The foregoing objects are achieved as is now described. A multiprocessor system bus protocol system and method for processing and handling a processor request within a multiprocessor system having a number of bus accessible memory devices that are snooping on at least one bus line. Snoop response groups which are groups of different types of snoop responses from the bus accessible memory devices are provided. Different transfer types are provided within each of the snoop response groups. A bus master device that provides a bus master signal is designated. The bus master device receives the processor request. One of the snoop response groups and one of the transfer types are appropriately designated based on the processor request. The bus master signal is formulated from a snoop response group, a transfer type, a valid request signal, and a cache line address. The bus master signal is sent to all of the bus accessible memory devices on the cache bus line and to a combined response logic system. All of the bus accessible memory devices on the cache bus line send snoop responses in response to the bus master signal based on the designated snoop response group. The snoop responses are sent to the combined response logic system. A combined response by the combined response logic system is determined based on the appropriate combined response encoding logic determined by the designated and latched snoop response group. The combined response is sent to all of the bus accessible memory devices on the cache bus line.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.